The present disclosure relates to integrated circuit (IC) interconnects, and more specifically, to methods of forming an interconnect with a chamferless via, and a related interconnect.
Integrated circuits include a number of interconnect layers that allow for electrical interconnection of devices in various layers such as transistors, resistors, capacitors, etc. Each interconnect layer typically includes wiring that laterally interconnects structures, or vias that vertically interconnect structures. Each interconnect layer typically includes a dielectric layer into which the wires and/or vias, which are collectively and individually referred to herein as interconnects, are formed. Each interconnect layer is typically separated by an etch stop layer that is used to control etching during formation of the interconnect layers.
Damascene is a process in which an interconnect pattern is first lithographically defined in a layer of dielectric, then metal is deposited to fill resulting wire trench openings or via openings, and then excess metal is removed by means of chemical-mechanical polishing (planarization). Dual damascene is a similar process in which interconnect patterns define wire trench openings and via openings together prior to metal deposition.
During dual damascene processing, a via preferably lands on a via or another conductive structure, e.g., a wire or device, in a lower interconnect layer. A challenge with this process is that the trench etching to create a wire trench opening for a wire can impact aspects of the via opening for the via, and hence the operation of the via. First, an enlarged chamfer can be created during trench etching that can cause a short of the via. The ability for an enlarged chamfer to create a short can be increased, for example: by an overlay error (OVL) in the mask patterning for via(s) and/or wire(s); a non-uniformity or an angle variation of the via(s); and/or a high voltage strip fail. Second, the trench etching coming after the via etching can create a via bumpout that when filled with metal can short the via to, for example, another wire above the via. In particular, the trench etching can erode the metal liner that can allow for the short. Even if a short does not immediately result, the occurrence of shorts can still be increased because of the increased chances of time dependent dielectric breakdown (TDDB) caused by the overlay error or liner erosion. These challenges may be more profound, for example, near a wafer edge when process non-uniformity (e.g., film thickness, etch rate) occurs. The issue may occur, for example, due to increased etch stop layer erosion during dielectric reactive ion etching (RIE) at the edge. However, the challenges can be observed in any interconnect layer.